1. Field of the Invention
The present invention relates to an interferometer for measuring shapes, and more particularly to an interferometer capable of being utilized to measure the coplanarity (identical planarity and flatness) of a plurality of linear circuit wires arranged with a high density on a substrate in various kinds of displays, such as a plasma display and EL, and a semiconductor wafer and the like.
2. Description of the Related Art
The increasing of the degree of integration, and an increase in the scale and area of display elements, such as a plasma display, and electronic parts and semiconductor elements and the like have been progressed, and the refining and lamination with the advance of the techniques needed for this progress of circuit wires are being forwarded. In a process for manufacturing such elements, the securing, etc. of a sectional area of wires, which are necessary for securing the insulation between wires, the preventing of the wires from being broken, the securing of the insulation between the laminated layers, and the operating of the elements properly are important problems.
The techniques for coating wires, which are formed on an element substrate by etching a metal film, with an insulating layer so as to secure the insulation between the wires, prevent the breaking of wires, secure the insulation between laminated layers of wires, and the like; flattening an upper surface of the insulating layer by polishing the same by a lapping machine and the like; and thereby solving the problems encountered in a lamination operation have been known well. In this method, it is necessary that the polishing operation be carried out as the thickness of an insulating layer on the wires is strictly controlled so as to secure the insulation between the wires and between the layers (refer to JP-A-8-240413).
However, in the method of forming wires by etching a metal film, an aspect ratio (ratio of the width of wires to the thickness of the metal film) becomes excessively large with the advancement of the refining of the wires. This makes it difficult to obtain a desired sectional shape of wires when the etching techniques are utilized. As a result, the securing of the sectional area of the wires needed to work the elements properly, and the occurrence of imperfect insulation and the like between the wires due to the remaining etched metal film become problems. In order to solve the problems, a process for making grooves for the wires in a film type insulator formed on the substrate in advance, forming a metal film on the insulator including the surface of the interior of the grooves, subjecting this metal film to a chemical and mechanical polishing process uniformly to the surface of the insulator, and thereby eliminating the metal on the insulator so as to leave only the metal in the grooves as wires has become to be employed. In this method, it is necessary that the depth of the grooves formed by the etching of the insulator be controlled with a high accuracy for the purpose of obtaining a sectional area required for the wiring operation (refer to JP-A-2002-048519).
Moreover, a means for forming a negative image of a wire pattern by photoresist members on a metal film formed on a semiconductor substrate, and forming wires by plating an upper surface of an exposed metal wire pattern with a metal, such as gold by a plating method is also known. In this method, plating current leakage occurs in a circumferential portion of the substrate to cause in some cases the thickness of a plated film in the central and circumferential portions to vary. Therefore, it is necessary that the height distribution of the upper surfaces of the metal wires with respect to that of the substrate or photoresist members be controlled (refer to JP-A-5-121403).
In order to carry out such a control operation, it is demanded that the coplanarity of a plurality of linear surfaces to be detected of not only the upper surfaces of the wires, bottom surfaces of the grooves or upper surfaces of plated metal wires but also an upper surface of an insulating layer, an upper surface of the substrate or the upper surfaces of photoresist members.
Methods of measuring the coplanarity of each linear surface to be detected and the flatness of the upper surface of a substrate by locally measuring the height of the upper surface of the substrate viewed from the linear surfaces to be detected and from a position between the linear surfaces to be detected, by using an interference spectroscopic film thickness gauge (JP-A-8-240413), a spot interference method (JP-A-2002-048519), an optical cutting method, a cofocal method, a shaded region measuring method using diagonal illumination (JP-A-2001-298036) and the like have heretofore been known.
However, such measuring methods need to set a plurality of measuring points, so that a lot of time is required to conduct measurement. Especially, these methods are not suited for the in-process measurement.
When the planarity of the substrate is excellent, the linear surfaces to be detected generally come to be flush with one another from a manufacturing stage therefor. Therefore, it is also conceivable that an interference fringe image corresponding to the shape of one flat surface constituting a plurality of linear surfaces to be detected be photographed by using an interferometer for measuring a surface shape, and that the coplanarity of each linear surface to be detected be determined by making an analysis of the same image. However, a virtual surface made of a plurality of linear surfaces to be detected is separated by insulators and the like existing between the linear surfaces to be detected, and does not form one continuous flat surface. The substrate surface or photoresist surface viewed from positions between the linear surfaces to be detected is also separated from each other by the linear surfaces to be detected, and does not form one continuous flat surface. Therefore, it is difficult to measure with a related art interferometer the general shape of the surface to be detected.